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ACTEL FPGA 1602显示，Verilog描述
资料介绍
ACTEL FPGA 1602显示，Verilog描述
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| Compare_4bit_74hc85/smartgen/smartgen.aws | 1KB | 2010-05-28 18:43:24 |
| Compare_4bit_74hc85/hdl/Compare_4bit_74hc85.v | 1KB | 2010-05-26 22:36:18 |
| Compare_4bit_74hc85/viewdraw/vf/project.lst | 1KB | 2010-05-28 18:43:26 |
| Compare_4bit_74hc85/viewdraw/viewdraw.ini | 2KB | 2010-05-28 18:43:26 |
| Compare_4bit_74hc85/simulation/modelsim.ini.sav | 1KB | 2010-05-26 22:20:36 |
| Compare_4bit_74hc85/simulation/modelsim.ini | 1KB | 2010-05-28 18:43:26 |
| Compare_4bit_74hc85/designer/impl1/Compare_4bit_74hc85.ide_des | 1KB | 2010-05-26 22:36:18 |
| Compare_4bit_74hc85/Compare_4bit_74hc85.prj | 2KB | 2010-05-28 18:44:52 |
| Compare_4bit_74hc85/真值表.bmp | 729KB | 2010-05-26 22:37:42 |
| Compare_4bit_74hc85/designer/impl1/simulation | 1KB | 2010-05-26 22:20:36 |
| Compare_4bit_74hc85/viewdraw/vf | 1KB | 2010-05-26 22:20:36 |
| ... | ||
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