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CAN总线的数据采集，FPGA到USB。Verilog HDL语言.
资料介绍
CAN总线的数据采集，FPGA到USB。Verilog HDL语言.
部分文件列表
| 文件名 | 大小 |
| can_exm1_sys/ | |
| can_exm1_sys/.lso | |
| can_exm1_sys/Untitled4 | |
| can_exm1_sys/_ngo/ | |
| can_exm1_sys/_ngo/netlist.lst | |
| can_exm1_sys/_stx_beh.prj | |
| can_exm1_sys/_xmsgs/ | |
| can_exm1_sys/_xmsgs/bitgen.xmsgs | |
| can_exm1_sys/_xmsgs/map.xmsgs | 1KB |
| can_exm1_sys/_xmsgs/ngdbuild.xmsgs | |
| can_exm1_sys/_xmsgs/par.xmsgs | 3KB |
| ... | |
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