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一种带自校准的Time interleave ADC设计
资料介绍
这是一种带自校准的四路复用Time interleave ADC的设计。讨论实现中遇到的问题,给出了Time interleave ADC的校准方法。通过校准,Time interleave ADC可以实现比较高的性能。对于高速ADC应用,Time interleave ADC是一个非常好的方向。但高速带来的面积挑战、性能挑战、功耗挑战也是一个持续的课题需要继续深入研究。
This is a design of a four-way multiplexing Time interleave ADC with self-calibration.The problems encountered in the implementation are discussed,and the calibration method of Time Interleave ADC is given.Time interleave ADC can achieve high performance through calibration.Time interleave ADC is a very good direction for high-speed ADC applications.However,the challenges of area,performance and power consumption brought by high-speed are also a continuing subject that needs further study.
部分文件列表
| 文件名 | 大小 |
| 一种带自校准的Time_interleave_ADC设计.pdf | 1M |
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