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基于门延时的数字TDC电路设计
资料介绍
为了扩大时间数字转换（Time to Digital Converter,TDC）的测量范围并提高其分辨率,确保测量结果的正确有效,提出了一种数字TDC电路的设计方法。采用与工艺无关的环形门延时单元的设计方法,缩小了电路规模,且可以方便地移植到其它系统中。通过Verilog HDL语言对该设计进行了RTL级的描述,最后通过了时序仿真和FPGA验证。该设计方法与现有设计方法相比,使用较少的逻辑资源达到了大量程高精度的测量要求,计数结果正确稳定。
In order to improve the measuring range of the TDC circuit and its resolution,to ensure that the measuring results are correct and effective,this paper puts forward a kind of digital TDC circuit design method.It can reduce the circuit scale and can be easily ported to other systems.This paper uses the language of Veriolg HDL to design the circuit in RTL level and passes the timing simulation and FPGA verification at last.It achieves the requirements of wide range and high precision by using the gate time delay method and reduce the logic resources consumption.The count results are correct and stable.
部分文件列表
| 文件名 | 大小 |
| 基于门延时的数字TDC电路设计.pdf | 226K |
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