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SystemVerilog验证方法实例random_generator

更新时间:2019-09-10 06:25:46 大小:4M 上传用户:sun2152查看TA发布的资源 标签:systemverilog 下载积分:1分 评价赚积分 (如何评价?) 打赏 收藏 评论(0) 举报

资料介绍

We have seen how to generate random numbers. But the numbers range from-

(2**32-1) to 2**32. Most of the time, the requirement don't need this range.

For example, take a memory. The address starts from 0 to some 1k or

1m. Cenerating a random address which DUT is not supporting is meaningless.

In verilog there are no constructs to constraint randomization. Fallowingexample demonstrated how to generate random number between 0 to 10. Using

% operation, the remainder of any number is always between 0 to 10.

The above example shows the generation of numbers from 0 to N. Some specification require the range to start from non Zero number. MIN +{$random}

%((MAX-MIN) will generate random numbers between MIN and MAX.


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SystemVerilog验证方法实例random_generator.pdf 4M

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