一种基于数据存储的流水SHA256硬件实现电路

提出了一种新型的基于数据存储的SHA256全流水数据迭代方式。在全流水SHA256结构中,数据压缩器中的状态寄存器每次更新时只需要计算A和E,而状态寄存器B-D和F-H则可以直接从前一轮中的A-C和E-G得到。且每轮新产生的A和E在经历四级流水传递后将不再被使用,因此A和E生命周期为4个时钟周期。在传统数据迭代的方式中,每次数据更新将会导致A-H共8组寄存器同时翻转。因此,为了减小寄存器的翻转次数,继而降低寄存器的翻转功耗,提出了一种存储方案,即采用锁存器存储每级新产生的A和E,当后级需要使用时,通过选择器选择前级锁存器存储的A和E数据,用于产生本级新的A和E。由此,在进行数据迭代时,每轮只有A和E两组存储器更新,从而可以降低电路的动态功耗。在所提方案中,采用锁存器代替触发器作为存储单元,同时通过由传输门构成的选择器来实现数据的选择。仿真结果表明:在28nm工艺下,采用数据存储代替寄存器翻转后的SHA256全流水结构功耗降低约27.5%,面积减少约49.2%。

A new method to realize full-pipelined SHA256 based on data storage is proposed. For the full-pipelined SHA256, only A and E need to be calculated each time when the status registers of the data compressor are updated, while B-D and F-H can be obtained directly from A-C and E-G of the previous round. Since A and E will no longer be used after they have been transmitted forward for four stages, the life cycles of each stage′s A and E are both 4 clock cycles. For the traditional pipeline structure, all status registers which are used to store A-H will be updated at the same time, which hence introduce a large dynamic power. Therefore, in order to reduce the numbers of registers, and then reduce the dynamic power of registers, this paper proposes a storage scheme, which uses latches to store each stage′s A and E. When the latter stage needs to use A and E of previous stage, it selects A and E stored in the latches of previous stages using MUXs. Therefore, only the values of two sets of latches(A and E) will update per stage, which can reduce the dynamic power consumption of the circuit. In the proposed scheme, latch is used instead of flip-flop as a storage unit, and data is selected by using MUXs which are composed of transfer gates. The proposed scheme is realized and verified using a 28 nm process, the simulation results show that when compared with traditional structure, the power consumption of the pipelined SHA256 using data storage scheme is reduced by about 27.5%, and the area is reduced by about 49.2%.