LKS32AT03x_用户手册_v1.47

LKS32AT03x_用户手册_v1.47 1 Document Convention 1.1 Register Read/Write Access RW Read/write, available for software read and write. RO Read-only, software can only read. WO Write-only, software can only write. The default value will be returned when reading this bit. RW1C Read and Write 1 to Clear. 1.2 Abbreviations Word: 32-bit data/instruction. Halfword: 16-bit data/instruction. Byte: 8-bit data. Double word: 64-bit data. ADC: Analog-Digital Converter DAC: Digital-Analog Converter BGP: Bandgap. Bandgap voltage reference WDT: Watch dog LSI: Low Speed Internal Clock, the 32KHz RC oscillator HSI: High Speed Internal Clock, the 4/8/12MHz RC oscillator PLL: Phase Lock Loop Clock, the PLL clock, which usually used as high-speed system clock POR: Power-On Reset. Reset signal generated when the chip system is powered on IAP (In-Application Programming): IAP means that the Flash of the microcontroller can be reprogrammed while the user program is (In-Circuit Programming): ICP means that you can use the JTAG protocol, SWD protocol or bootloader to program the Flash of the microcontroller when the device is installed on the Subscriber Circuit Board. CW: Clockwise CCW: Counterclockwise Option bytes: Option byte, the MCU configuration byte saved in Flash. 2 System Overview 2.1 Introduction LKS32MC03x series MCUs are extremely cost-effective and compact, equipped with a 48MHz Cortex-M0 core, as well as necessary analog and peripheral resources. The module integration is more refined and widely suitable for lightweight applications. 2.2 Feature o 48MHz 32-bit RISC kernel, 32bit hardware division coprocessor o 4-channel DMA o Low power sleep mode o -40~105°C industrial operating temperature range o 2.5V~5.5V single power supply, internally integrated digital power supply LDO o Super antistatic and group pulse ability 2.2.1Storage o 16/32kB Flash, data anti-theft function o 4kB RAM 2.2.2Clock o Built-in 4MHz high-precision RC clock, with full temperature range accuracy ±1% o Built-in 32kHz low speed clock for low power mode o Internal PLL can provide up to 48MHz clock 2.2.3Peripheral Clock o 1-channel UART o 1-channel SPI o 1-channel IIC o Universal 16/32 bit Timer supports capturing and edge-aligned PWM o Motor control dedicated PWM module supports 6 PWM outputs, and the dead zone can be configured o Hall signal interface supports speed measurement and debouncing o Hardware Watchdog o 26-channel GPIO 2.2.4Analog Module o Built-in 12bit SAR ADC, 1Msps sampling and conversion rate, up to 11 channels o Built-in 1 OPA. Differential PGA mode is available o Built-in 2 comparators o Built-in 8bit DAC as internal comparator input o 1.2V 0.5% built-in linear regulator o Built-in low power LDO and power monitoring circuit o Built-in high-precision, low-temperature drift and high-frequency RC clock 3 Address Space The data bytes are stored in memory in little-endian format. The lowest address byte in a word is considered the least significant byte of the word, and the highest address byte is the most significant byte. All other unallocated on-chip memory and external memory are reserved address spaces.