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阵列探测器L1触发系统加法电路优化设计

更新时间:2020-09-13 05:34:59 大小:272K 上传用户:守着阳光1985查看TA发布的资源 标签:阵列探测器 下载积分:2分 评价赚积分 (如何评价?) 打赏 收藏 评论(0) 举报

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针对兰州重离子加速器外靶终端硅微条阵列探测器L1触发系统,设计了一个基于Xilinx7系列FPGA芯片的改进加法逻辑电路,利用快速进位链结构,对加法电路模块进行优化.对优化后加法电路结构和同类传统加法电路比较,并对逻辑时延进行和结构性能建模分析.仿真和测试结果表明:优化后模块逻辑时延3 ns左右,相比传统加法逻辑,系统死时间低,有效采集事例率高,能够满足L1触发系统的要求.

Focused on the level 1 sub - trigger system in Silicon, micro - strip array detector of the Cooling Stor- age Ring on the Heavy Ion Research Facility in Lanzhou (HIRFL - CSR), in this paper, based on the structural features of Xilinx 7 series FPGA chip, an improved design of logic circuit for the adder module is proposed, fast carry logic adder is employed and a new trigger judgment circuit is developed. Compared with the traditional adder circuit and the optimized, modeling analyses of structural performance and logic dead - time, the circuit was simulated and tested. The dead time of improved module is reduced to about 3 ns. Compared with oth- er types of adder circuit structures, the signal processing time of new trigger judgment circuit is reduced...

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阵列探测器L1触发系统加法电路优化设计.pdf 272K

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