Intel FPGA Integer Arithmetic IP Cores 用户指南

Intel FPGA Integer Arithmetic IP Cores User Guide

1 Intel FPGA Integer Arithmetic IP Cores........................................................................... 5

2 LPM_COUNTER (Counter) IP Core.................................................................................... 7

2.1 Features................................................................................................................7

2.2 Verilog HDL Prototype............................................................................................. 8

2.3 VHDL Component Declaration...................................................................................8

2.4 VHDL LIBRARY_USE Declaration............................................................................... 9

2.5 Ports.....................................................................................................................9

2.6 Parameters.......................................................................................................... 10

3 LPM_DIVIDE (Divider) IP Core...................................................................................... 12

3.1 Features.............................................................................................................. 12

3.2 Verilog HDL Prototype........................................................................................... 12

3.3 VHDL Component Declaration................................................................................. 13

3.4 VHDL LIBRARY_USE Declaration............................................................................. 13

3.5 Ports................................................................................................................... 13

3.6 Parameters.......................................................................................................... 14

4 LPM_MULT (Multiplier) IP Core...................................................................................... 16

4.1 Features.............................................................................................................. 16

5.6 Parameters.......................................................................................................... 24

12 ALTMULT_COMPLEX (Complex Multiplier) IP Core....................................................... 86

12.1 Complex Multiplication......................................................................................... 86

12.2 Canonical Representation..................................................................................... 87

12.3 Conventional Representation................................................................................ 87

12.4 Features............................................................................................................ 88

12.5 Verilog HDL Prototype..........................................................................................88

12.6 VHDL Component Declaration............................................................................... 89

12.7 VHDL LIBRARY_USE Declaration............................................................................89

12.8 Signals.............................................................................................................. 89

12.9 Parameters........................................................................................................ 90

13 ALTSQRT (Integer Square Root) IP Core......................................................................93

13.1 Features............................................................................................................ 93

13.2 Verilog HDL Prototype..........................................................................................93

13.3 VHDL Component Declaration............................................................................... 94

13.4 VHDL LIBRARY_USE Declaration............................................................................94

13.5 Ports................................................................................................................. 94

13.6 Parameters........................................................................................................ 95

14 PARALLEL_ADD (Parallel Adder) IP Core..................................................................... 96

14.1 Feature..............................................................................................................96

14.2 Verilog HDL Prototype..........................................................................................96

14.3 VHDL Component Declaration............................................................................... 97

14.4 VHDL LIBRARY_USE Declaration............................................................................97

14.5 Ports................................................................................................................. 97

14.6 Parameters........................................................................................................ 98

A Integer Arithmetic IP Cores User Guide Document Archives.......................................... 99

B Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide.....100