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一种全数字半速率鉴相器的设计
资料介绍
鉴相器是高速时钟数据恢复环路的关键电路，其性能的优劣直接影响了整个系统的工作。通过系统分析，提出了一种全数字半速率鉴相器设计方案，按照全定制设计流程采用SMIC 0.18μm CMOS混合信号工艺完成了电路的设计、仿真。结果表明该电路在2.5 Gb/s收发器电路中可以稳定可靠地工作。
The phase detector is a critical part of high-speed clock and data recovery circuit. Its performance has great influence on the whole system. According to a system analysis,a design scheme of all-digital half-rate phase detector is proposed in this paper. According to the full custom design flow,the circuit design and simulation were accomplished with the process of SMIC 0.18 μm CMOS mixed-signal. The simulation result shows that the circuit can work stably in the 2.5 Gb/s transceiver circuit.
部分文件列表
| 文件名 | 大小 |
| 一种全数字半速率鉴相器的设计.pdf | 587K |
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