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FPGA-DDR3电路设计与测试验证

更新时间：2020-10-27 20:48:16 大小：1M 上传用户：gsy幸运查看TA发布的资源 标签：fpga 电路设计 ddr3 下载积分：1分评价赚积分（如何评价?）收藏评论(0) 举报

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DDR3 SDRAM作为FPGA的高速数据存储器,在嵌入式信号处理计算机中有广泛的应用。详细介绍了FPGA-DDR3电路的设计方法,包括原理设计、供电设计、信号完整性设计等。对DDR3硬件链路的信号进行了测量分析,并结合DDR3的访存特性,设计测试向量,对DDR3的读写性能进行了详细测试,结果表明:FPGA-DDR3电路的各类信号均符合JESD79-3规范要求,读写带宽满足嵌入式信号处理的应用需求。

DDR3 SDRAM as a high-speed date memory of FPGA,it is widely used in embedded signal processing computer.The design method of FPGA-DDR3 circuit is introduced in detail,including schematic design,power supply design,signal integrity design and etc.Measuring and analyzing the signal link of DDR3 hardware,and base on the characteristics of DDR3,designing test vectors,we test the read-write performance of DDR3 in detail.The results show that the signal characteristics of FPGA-DDR3 circuit are fully compatible with JESD79-3 specification,and read-write bandwidth meets the requirements of embedded signal processing application.