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一种适于FPGA芯片的SRAM单元及外围电路设计
资料介绍
静态存储器（SRAM）功耗是整个芯片功耗的重要组成部分,并且大规模SRAM的仿真在芯片设计中也相当费时。提出了一种基于40 nm CMOS工艺、适用于FPGA芯片的SRAM单元结构,并为该结构设计了外围读写控制电路。仿真结果表明,该结构的SRAM单元在保证正确的读写操作下,静态漏电电流远远小于同工艺下普通阈值CMOS管构造的SRAM单元。同时,为了FPGA芯片设计时大规模SRAM功能仿真的需要,为SRAM单元等编写了verilog语言描述的行为级模型,完成了整个设计的功能验证。
SRAM cell power contributes a key part of the whole chip power consumption, and the simulation of a large scale of SRAM will cost long time. In the paper, present a SRAM cell with low leakage current for FPGA based on 40 nm technology, and also design write/read control circuit for the cell. The simulation result shows that the cell which present works with lower leakage current than normal threshold voltage CMOS SRAM. In particular, build the behavioral model of the SRAM cell and the other driving circuits using the Verilog language for the convenient of the whole chip simulation.
部分文件列表
| 文件名 | 大小 |
| 一种适于FPGA芯片的SRAM单元及外围电路设计.pdf | 793K |
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