推荐星级：
- 1
- 2
- 3
- 4
- 5
针对FPGA优化的高分辨率时间数字转换阵列电路
资料介绍
介绍一种针对FPGA优化的时间数字转换阵列电路。利用FPGA片上锁相环对全局时钟进行倍频与移相，通过时钟状态译码的方法解决了FPGA中延迟的不确定性问题，完成时间数字转换的功能。在Ahera公司的FPGA上验证表明，本时间数字转换阵列可达1．73ns的时间分辨率。转换阵列具有占用资源少，可重用性高，可以作为IP核方便地移植到其他设计中。
An FPGA-optimized high resolution time-to-digital converter array is proposed. In this design, we adapt the onchip PLL as the frequency double circuit and the clock phase shifter. We use the method of clock state decoding to solve the delay uncertainty for FPGA, thereby fulfill the time to digital convert. The circuit has been implemented via FPGA produced by Altera Corp. The result shows that the time resolution is 1.73 ns. It enjoys the advantages of less resource usage, high reusability and easy implantation as IP cores.
部分文件列表
| 文件名 | 大小 |
| 针对FPGA优化的高分辨率时间数字转换阵列电路.pdf | 1M |
相关下载
- 华为模块电源管理设计指导-(V100R001_02 Chi...
- 华为LGA模块PCB设计指导_V2.0_20150126.pdf
- HUAWEI Module USB Interface Descriptor Gui...
- HUAWEI ME909s-821 LTE LGA模块硬件指南V100R...
- HUAWEI ME909s-821 LTE LGA Module Acceptanc...
- HUAWEI 30 mm x 30 mm LGA Module Hardware M...
- HUAWEI 30 mm x 30 mm LGA Module Developmen...
- Altium_Designer_规则设置三例.pdf
- STM32F407产品技术培训-DSP库及其例程
- STM32F407产品技术培训-2.浮点单元.pdf
全部评论(0)