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FPGA开发入门的Verilog HDL程序
资料介绍
FPGA开发入门的Verilog HDL程序
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| flowled/db/add_sub_msh.tdf | 6KB | 2008-07-22 00:59:18 |
| flowled/db/flowled.(0).cnf.cdb | 3KB | 2008-07-22 02:07:50 |
| flowled/db/flowled.(0).cnf.hdb | 1KB | 2008-07-22 02:07:50 |
| flowled/db/flowled.analyze_file.qmsg | 2KB | 2008-07-22 00:55:10 |
| flowled/db/flowled.asm.qmsg | 2KB | 2008-07-22 02:08:36 |
| flowled/db/flowled.cbx.xml | 1KB | 2008-07-22 02:08:30 |
| flowled/db/flowled.cmp.cdb | 14KB | 2008-07-22 02:08:38 |
| flowled/db/flowled.cmp.hdb | 6KB | 2008-07-22 02:08:38 |
| flowled/db/flowled.cmp.kpt | 1KB | 2008-07-22 02:08:34 |
| flowled/db/flowled.cmp.logdb | 1KB | 2008-07-22 02:08:34 |
| flowled/db/flowled.cmp.rdb | 16KB | 2008-07-22 02:08:38 |
| ... | ||
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