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FPGA开发板上的JTAG-UART完成的工程设计
资料介绍
FPGA开发板上的JTAG-UART完成的工程设计
部分文件列表
文件名 | 文件大小 | 修改时间 |
JTAG_UART/.metadata/.lock | 1KB | 2009-06-01 13:54:56 |
JTAG_UART/.metadata/.log | 16KB | 2009-06-01 15:25:58 |
JTAG_UART/.metadata/.plugins/com.altera.nj.ui/dialog_settings.xml | 1KB | 2009-06-01 14:32:00 |
JTAG_UART/.metadata/.plugins/org.eclipse.cdt.core/.log | 1KB | 2009-06-01 15:43:58 |
JTAG_UART/.metadata/.plugins/org.eclipse.cdt.core/1247327250.index | 40KB | 2009-06-01 14:28:36 |
JTAG_UART/.metadata/.plugins/org.eclipse.cdt.core/2081678753.index | 32KB | 2009-06-01 14:18:30 |
JTAG_UART/.metadata/.plugins/org.eclipse.cdt.core/2475800202.index | 121KB | 2009-06-01 14:28:08 |
JTAG_UART/.metadata/.plugins/org.eclipse.cdt.core/3216897728.index | 121KB | 2009-06-01 14:18:30 |
JTAG_UART/.metadata/.plugins/org.eclipse.cdt.core/savedIndexNames.txt | 1KB | 2009-06-01 15:43:58 |
JTAG_UART/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c | 1KB | 2009-06-01 13:56:00 |
JTAG_UART/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp | 1KB | 2009-06-01 13:56:00 |
... |
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