嵌入式常用IP手册

嵌入式常用IP手册，

1. Introduction................................................................................................................. 19

1.1. Tool Support....................................................................................................... 19

1.2. Device Support....................................................................................................20

1.3. Document Revision History for Embedded Peripherals IP User Guide........................... 21

2. Avalon-ST Multi-Channel Shared Memory FIFO Core.....................................................24

2.1. Core Overview.....................................................................................................24

2.2. Performance and Resource Utilization..................................................................... 24

2.3. Functional Description.......................................................................................... 25

2.3.1. Interfaces...............................................................................................26

2.3.2. Operation............................................................................................... 26

2.4. Parameters......................................................................................................... 27

2.5. Software Programming Model................................................................................28

2.5.1. HAL System Library Support......................................................................28

2.5.2. Register Map...........................................................................................28

2.6. Avalon-ST Multi-Channel Shared Memory FIFO Core Revision History..........................29

3. Avalon-ST Single-Clock and Dual-Clock FIFO Cores.......................................................30

3.1. Core Overview.....................................................................................................30

3.2. Functional Description.......................................................................................... 30

3.2.1. Interfaces...............................................................................................31

3.2.2. Operating Modes......................................................................................31

3.2.3. Fill Level.................................................................................................32

3.2.4. Thresholds..............................................................................................32

3.3. Parameters......................................................................................................... 33

3.4. Register Description............................................................................................. 33

3.5. Avalon-ST Single-Clock and Dual-Clock FIFO Core Revision History............................34

4. Avalon-ST Serial Peripheral Interface Core...................................................................36

4.1. Core Overview.....................................................................................................36

4.2. Functional Description.......................................................................................... 36

4.2.1. Interfaces...............................................................................................36

4.2.2. Operation............................................................................................... 37

4.2.3. Timing....................................................................................................38

4.2.4. Limitations..............................................................................................38

4.3. Configuration...................................................................................................... 38

4.4. Avalon-ST Serial Peripheral Interface Core Revision History....................................... 38