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Cyclone V Device Overview
资料介绍
The Cyclone® V devices are designed to simultaneously accommodate the shrinking power consumption,
cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume and
cost-sensitive applications.
Enhanced with integrated transceivers and hard memory controllers, the Cyclone V devices are suitable for
applications in the industrial, wireless and wireline, military, and automotive markets.
Related Information
Cyclone V Device Handbook: Known Issues
Lists the planned updates to the Cyclone V Device Handbook chapters.
Advantage Supporting Feature
• Built on TSMC's 28 nm low-power (28LP) process technology and includes
an abundance of hard intellectual property (IP) blocks
• Up to 40% lower power consumption than the previous generation device
Lower power consumption
• 8-input adaptive logic module (ALM)
• Up to 13.59 megabits (Mb) of embedded memory
• Variable-precision digital signal processing (DSP) blocks
Improved logic integration and
differentiation capabilities
• 3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers
• Hard memory controllers
Increased bandwidth capacity
• Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard
IP, and an FPGA in a single Cyclone V system-on-a-chip (SoC) FPGA
• Supports over 128 Gbps peak bandwidth with integrated data coherency
between the processor and the FPGA fabric
Hard processor system (HPS)
with integrated ARM®
Cortex™-A9MPCoreprocessor
• Requires only two core voltages to operate
• Available in low-cost wirebond packaging
• Includes innovative features such as Configuration via Protocol (CvP) and
partial reconfiguration
部分文件列表
| 文件名 | 大小 |
| Cyclone_V_Device_Overview.pdf | 724K |
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