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四路串行CMOS复接器的设计实现
资料介绍
通信系统中,数字复接是提高带宽利用率的一项重要技术,将多路并行低速信号转变为高比特率的串行数字流。首先使用Cadence软件仿真基本门级CMOS电路,通过自下而上的FPGA设计方法和Verilog硬件描述语言,设计四路串行复接器的功能组成模块,完成QuartusⅡ平台上的可综合验证。最后提出了复接器CMOS集成电路的设计思路。
Digital multiplexing is an important technique for improving bandwidth utilization in communication system by transferring multi- channel parallel low rate signals into a serial high rate one. This article gives the simulation of basic gate-level CMOS circuit using Cadence software, and describes each functional sub-module of four-channel serial multiplexer by Verilog hardware description language. Quartus II is used for logic synthesis and verification under bottom-up FPGA design method, and finally the design idea of CMOS multiplexer IC is proposed.
部分文件列表
| 文件名 | 大小 |
| 四路串行CMOS复接器的设计实现.pdf | 832K |
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