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CAN总线的数据解码设计与实现
资料介绍
针对目前标准定制的CAN解码器芯片接口固定、通用性差、不能兼容且不易集成到已有嵌入式系统，以及实现额外功能需外接电路的问题。将CAN解码器设计成软核，在单片FPGA中构建CAN总线系统来解决上述不足，同时在FPGA的剩余资源上集成其他自行设计的数字电路，有效减少外围芯片的数量，提高CAN解码器的性能、效率。
In view of the present standard custom CAN decoder chip interface is fixed, poor universality, not compatible and integrated into the existing embedded systems, some problems needed to be an external circuit and additional functions. Will CAN decoder into soft core design, build in single FPGA CAN bus system to solve the above deficiencies, at the same time remaining in the FPGA resources integration other digital circuit design, effectively reduce the number of peripheral chips, improve CAN decoder performance and efficiency.
部分文件列表
| 文件名 | 大小 |
| CAN总线的数据解码设计与实现.pdf | 796K |
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