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AP6xxx 参考电路设计

更新时间:2019-09-16 14:26:58 大小:316K 上传用户:+vx15059162534查看TA发布的资源 标签:ap6xxx参考电路设计wifi 下载积分:2分 评价赚积分 (如何评价?) 打赏 收藏 评论(0) 举报

资料介绍


  1. AP6xxx参考电路设计

  2. AP6xxx评估板

  3. 规格书


部分文件列表

文件名 大小
AP6xxx_Pin2Pin_Reference_Design_Circuit_For_Q42142951.pdf 316K

部分页面预览

(完整内容请下载后查看)
A
B
C
D
E
VDD_1V8  
AP6xxx Pin2Pin Reference Design Circuit  
R23  
0R  
CLK_REQ  
When using AP6212A, R23 placement, R22/C18 NC.  
Connected to HOST I/O 1V8  
R22  
C18  
0R/NP  
VDD_1V8  
4
3
2
1
When using AP6476, R22/23 placement, R23 NC.  
4
3
2
1
SDIO_CMD  
SDIO_D0  
4.7uF/NP  
SDIO_D1  
SDIO_D2  
When using AP6181/ AP6210/ AP6212/ AP6330/  
AP6335/ AP6255, R23/R22/C18 NC, pin5,pin8 floating.  
WiFi ANT  
SDIO_D3  
(VBAT range3.0V~4.8V, 400 mA norminal,  
450~850 mA maximum)  
WLAN  
VBAT  
SDIO_CLK  
WL_HOST_WAKE  
WL_REG_ON  
CLK_REQ  
R6  
0R  
C1  
AP6234 PIN5 &PIN8 for LTE COEX. If you don't use, you can floating.  
C2  
NP  
4.7uF  
C3  
10pF  
FM RX reference circuit  
R80  
R81  
10K  
10K  
R71  
FB1  
VDD_1V8  
50 Ohm RF trace  
FM_ANT  
BT_HOST_WAKE  
BT_WAKE  
BT_GPS_RST_N  
75R-BEAD  
0R  
FB2  
UART_TXD  
UART_RXD  
UART_CTS_N  
UART_RTS_N  
PCM_CLK  
PCM_SYNC  
PCM_IN  
PCM_OUT  
HOST_UART_RXD  
HOST_UART_TXD  
U1  
AP6xxx  
HOST_UART_RTS_N  
HOST_UART_CTS_N  
HOST_PCM_CLK  
HOST_PCM_SYNC  
HOST_PCM_OUT  
HOST_PCM_IN  
1.8K-BEAD  
R82  
BT/FM  
AUDIO OUT  
C24  
1uF  
J1  
10K/NC  
2
1
1
AUD_R  
AUDIO_JACK  
1
47  
46  
45  
4
3
2
C23  
1uF  
N_VDDSWP_IN  
N_VDDSWP_OUT  
N_VDDSWPIO  
IN/OUT must be cross  
2
AUD_L  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
WL_REG_ON  
WL_HOST_WAKE  
SDIO_D2  
WL_REG_ON  
WL_HOST_WAKE  
SDIO_DATA_2  
SDIO_DATA_3  
SDIO_DATA_CMD  
SDIO_DATA_CLK  
SDIO_DATA_0  
SDIO_DATA_1  
GND  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
UART_CTS_N  
UART_RXD  
UART_TXD  
UART_CTS_N  
UART_RXD  
UART_TXD  
UART_RTS_N  
TX1  
SDIO_D3  
Trace width minimum >12mil  
SDIO_CMD  
SDIO_CLK  
SDIO_D0  
UART_RTS_N  
TX2  
SDIO_D1  
N_REG_PU  
N_I2C_SCL  
GND  
N_I2C_SDA  
BT_RST_N  
VIN_LDO_OUT  
VDDIO  
EXTLNA_EN  
R79  
0R/NP  
VDD_1V8  
BT_GPS_RST_N  
When using AP6476/AP6251, R79 placement  
C15  
4.7uF  
32.768KHz  
S_CLOCK  
Power Inductor  
L3  
Rated Current 1A  
4.7uH  
GPS ANT  
32.768KHz  
C16  
4.7uF  
U8  
C27  
6
5
4
1
2
3
RFOUT  
ENABLE  
VCC  
GND  
GND  
RFIN  
L5  
C28  
EXTLNA_EN  
VDD_1V8  
10pF  
6.8nH  
470pF  
1. Using AP6181/AP6212A/AP6330/AP6234,  
RL1/RL2 NC,  
C25  
33nF  
MAX2659/BGU7005  
RL1  
RL2  
R59  
VDD_1V8  
2. Using AP6210/AP6476,  
RL1 placement, RL2 NC,  
0R/NP  
MCLK_IN  
R77  
3. Using AP6335, RL1 NC,  
PL2 Placement for SDIO3.0  
(VIO must be 1.8V)  
Frame A  
0R/NP  
R13  
0R  
U7  
NL27WZU04 (SOT-363)  
6
5
4
1
2
3
MCLK_IN  
OUT Y1  
Vcc  
IN A1  
GND  
IN A2  
Using AP6210, Frame A & Frame B placement,  
R47/R48 and Frame C NC and connect to module pin 30  
VDD_1V8  
4. Using AP6255, RL1/RL2 no placement,  
default =1.8V  
for SDIO3.0,  
OUT Y2  
R10  
560K  
RL2 placement for SDIO 2.0  
Using AP6181/AP6212(A)/AP6330/AP6335/AP6255/AP6234,  
Frame B Placement,  
VDD_1V8  
Frame C  
R47  
R48  
FrameA & Frame C NC  
and connect to module pin 10,11  
XTAL_IN  
XTAL_OUT  
X2  
0R/NP  
0R/NP  
TCXO 26MHz (2520)  
Y3  
26MHz (3225)  
R12  
C22  
1uF  
4
3
1
R72  
0R  
100R  
VCC GND  
2
MCLK_IN  
OUT GND  
1
3
Using AP6234/AP6255/AP6335,  
Y3 change to 37.4MHz.  
1
3
C11  
C9  
27pF  
27pF  
Using AP6476/AP6251, Frame A& Frame B NC.  
Connect to module's pin 30.  
Frame B  
AP6476 AP6251 AP6452 AP6251U  
AP6234 AP6255 AP6335 AP6256 AP6441  
AP6181 AP6212 AP6330 AP6210 AP6236  
Serial 12*12mm/LGA-44  
A
B
C
D

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