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高速设计操作指南

更新时间:2018-11-19 10:23:11 大小:586K 上传用户:z00查看TA发布的资源 标签:高速设计 下载积分:2分 评价赚积分 (如何评价?) 打赏 收藏 评论(0) 举报

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When routing for high speed it’s also extremely important to apply a Routing Topology. The topology of a net is the arrangement or pattern of the pin-to-pin connections. By default, pin-to-pin connections of each net are arranged to give the shortest overall connection length. A topology can be applied to a net for a variety of reasons. For high speed designs where signal reflections must be minimized, the net is arranged with a daisy chain topology. However, for ground nets, a star topology could be applied, to ensure that all tracks come back to a common point.

DDR2 (and some situations in DDR3) can employ “balanced-T” or “branch matched” topology. While DDR3 and DDR4 introduced “fly-by” topology. In “fly-by” topology, Address/Control/Clock signals are routed sequentially from one SDRAM to the next, which eliminates reflections. 



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文件名 大小
Altium-WP-High-Speed-Design-And-Xsignals.pdf 586K

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