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Altera推荐Verilog HDL代码风格

更新时间：2020-06-29 08:09:47 大小：717K 上传用户：xzxbybd查看TA发布的资源 标签：verilog hdl 下载积分：2分 评价赚积分 （如何评价?） 打赏 收藏 评论(0) 举报

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Altera推荐Verilog HDL代码风格：


This chapter provides Hardware Description Language (HDL) coding style

recommendations to ensure optimal synthesis results when targeting Altera® devices.

HDL coding styles can have a significant effect on the quality of results that you

achieve for programmable logic designs. Synthesis tools optimize HDL code for both

logic utilization and performance; however, synthesis tools have no information

about the purpose or intent of the design. The best optimizations often require

conscious interaction by you, the designer.

This chapter includes the following sections:

■ “Using the Quartus II Templates” on page 13–2

■ “Using Altera Megafunctions” on page 13–3

■ “Instantiating Altera Megafunctions in HDL Code” on page 13–3

■ “Inferring Multiplier and DSP Functions from HDL Code” on page 13–5

■ “Inferring Memory Functions from HDL Code” on page 13–13

■ “Coding Guidelines for Registers and Latches” on page 13–44

■ “General Coding Guidelines” on page 13–54

■ “Designing with Low-Level Primitives” on page 13–74

f For additional guidelines about structuring your design, refer to the Design

Recommendations for Altera Devices and the Quartus II Design Assistant chapter in

volume 1 of the Quartus II Handbook. For additional handcrafted techniques you can

use to optimize design blocks for the adaptive logic modules (ALMs) in many Altera

devices, including a collection of circuit building blocks and related discussions, refer

to the Advanced Synthesis Cookbook.

f The Altera website also provides design examples for other types of functions and to

target specific applications. For more information about design examples, refer to the

Design Examples page and the Reference Designs page on the Altera website.


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