Xilinx PCIE IP核：包括DDR2 Memory Interface ML555开发板

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Xilinx PCIE IP核：包括DDR2 Memory Interface ML555开发板

文件名	文件大小	修改时间
rtl/pcie_dma_top.v	29KB	2008-07-01 11:10:22
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top.v	8KB	2007-09-05 11:18:12
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top_black_box.v	2KB	2007-09-05 11:18:10
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top_ctrl_0.v	32KB	2007-09-05 11:18:10
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top_ddr2_top_0.v	8KB	2007-09-05 11:18:10
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top_idelay_ctrl.v	1KB	2007-09-05 11:18:10
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top_infrastructure.v	6KB	2008-05-29 14:28:32
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top_mem_if_top_0.v	10KB	2007-09-05 11:18:10
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top_phy_calib_0.v	48KB	2007-09-05 11:18:10
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top_phy_ctl_io_0.v	6KB	2007-09-05 11:18:10
rtl/pcie_userapp_wrapper/ddr2_memory_interface/rtl/mem_interface_top_phy_dm_iob.v	1KB	2007-09-05 11:18:10
...