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基于Verilog的简易逻辑分析仪，已经过调试
资料介绍
基于Verilog的简易逻辑分析仪，已经过调试
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| luojiyi_demo/db/altsyncram_2jg1.tdf | 12KB | 2011-01-08 14:58:38 |
| luojiyi_demo/db/altsyncram_8mk1.tdf | 17KB | 2011-04-01 20:54:42 |
| luojiyi_demo/db/luojiyi_demo.(0).cnf.cdb | 12KB | 2011-04-01 20:54:42 |
| luojiyi_demo/db/luojiyi_demo.(0).cnf.hdb | 3KB | 2011-04-01 20:54:42 |
| luojiyi_demo/db/luojiyi_demo.(1).cnf.cdb | 2KB | 2011-01-08 14:58:38 |
| luojiyi_demo/db/luojiyi_demo.(1).cnf.hdb | 1KB | 2011-01-08 14:58:38 |
| luojiyi_demo/db/luojiyi_demo.(2).cnf.cdb | 1KB | 2011-01-08 14:58:38 |
| luojiyi_demo/db/luojiyi_demo.(2).cnf.hdb | 1KB | 2011-01-08 14:58:38 |
| luojiyi_demo/db/luojiyi_demo.(3).cnf.cdb | 1KB | 2011-01-08 14:58:38 |
| luojiyi_demo/db/luojiyi_demo.(3).cnf.hdb | 1KB | 2011-01-08 14:58:38 |
| luojiyi_demo/db/luojiyi_demo.(4).cnf.cdb | 2KB | 2011-04-01 20:54:42 |
| ... | ||
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