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基于电路结构的测试移位功耗优化方法
资料介绍
研究了扫描结构和测试功耗优化技术,考虑到现有的修改扫描单元结构降低测试移位功耗的方法存在冗余开销的问题,提出一种新的基于电路结构的测试移位功耗优化方法。该方法充分利用芯片内部的电路结构,通过分析扫描单元的扇出结构及其控制值,并根据分析结果和权重分配规则动态规划扫描单元的优化顺序,减少处理扫描单元的数量,避免产生冗余的测试开销。同时保证组合逻辑在移位过程中保持不翻转或者尽量不翻转,从而达到降低测试移位功耗的目的。在ITC’99基准电路上的实验结果表明,采用上述优化方法后组合逻辑的移位功耗降低了8.18%到96.98%,时序逻辑的移位功耗降低了41.92%到71.74%,与现有修改扫描单元的方法相比,面积开销节省了6.71%到20.95%。
The scan structure and test-power optimization are studied,and a new test-shift-power optimization method based on circuit structure is proposed.To reduce the number of modified scan cells and delete redundant test cost existing in test-shift-power reduction methods, the new method makes full use of inner structure of circuit , analyses fanouts and control value of scancells, and dynamically programs optimized order of scan cells according to analysis results and weight allocation rules. During shift procedure,combinational logic elements can be kept still to reduce test-shift-power further. The results of the test conducted on ITC’99 platform demonstrat that the shift-power of combinational logic elements is reduced by 8.18% to 96.98% and that of sequential logic elements is reduced by 41.92% to 71.74%. The cost of area is reduced by 6.71% to 20.95% compared with the existing methods based on modifying scan cells.
部分文件列表
| 文件名 | 大小 |
| 基于电路结构的测试移位功耗优化方法.pdf | 2M |
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