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FPGA设计三人表决器数码管显示实验Verilog源码Quartus工程文件
资料介绍
FPGA设计三人表决器数码管显示实验Verilog源码Quartus工程文件
部分文件列表
| 文件名 | 大小 |
| A4_Vote4/ | |
| A4_Vote4/A4_Vote4.qpf | 1KB |
| A4_Vote4/A4_Vote4.qsf | 5KB |
| A4_Vote4/A4_Vote4.qws | 1KB |
| A4_Vote4/A4_Vote4.v | 3KB |
| A4_Vote4/A4_Vote4.v.bak | 3KB |
| A4_Vote4/db/ | |
| A4_Vote4/db/.cmp.kpt | |
| A4_Vote4/db/A4_Vote4.(0).cnf.cdb | 1KB |
| A4_Vote4/db/A4_Vote4.(0).cnf.hdb | 1KB |
| A4_Vote4/db/A4_Vote4.ace_cmp.bpm | 1KB |
| ... | |
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