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基于FPGA的线阵CCDTCD1501D驱动时序电路的设计
资料介绍
针对电荷耦合器件CCD在进行图像扫描时需要稳定的外部驱动电路支持才能工作,本文介绍了利用Verilog HDL（硬件描述语言）编写TCD1501D型号线阵CCD驱动时序的实现方法,并对工作时序做了分析,还详细介绍了用Verilog HDL完成驱动时序的源代码,最后利用Modelsim进行仿真验证。
For charge-coupled device can work properly in the support of a stable external driving circuit when their image scanning,A realization methed in design of drive program for linear CCD Verilog HDL（a kind of hardware description language）is introduced and working signal of TCD1501D is analyzed,and the source code to complete the drive order with Verilog HDL is also discussed.Finally,simulated verification is made using the development software of Moledsim.
部分文件列表
| 文件名 | 大小 |
| 基于FPGA的线阵CCDTCD1501D驱动时序电路的设计.pdf | 505K |
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