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FPGA实现串口通信实验,用verilog实现串口的发送和接收数据
资料介绍
FPGA实现串口通信实验,用verilog实现串口的发送和接收数据 |
部分文件列表
文件名 | 大小 |
uart_verilog/ | |
uart_verilog/db/ | |
uart_verilog/db/logic_util_heursitic.dat | 5KB |
uart_verilog/db/my_uart_top.(0).cnf.cdb | 1KB |
uart_verilog/db/my_uart_top.(0).cnf.hdb | 1KB |
uart_verilog/db/my_uart_top.(1).cnf.cdb | 2KB |
uart_verilog/db/my_uart_top.(1).cnf.hdb | 1KB |
uart_verilog/db/my_uart_top.(2).cnf.cdb | 5KB |
uart_verilog/db/my_uart_top.(2).cnf.hdb | 1KB |
uart_verilog/db/my_uart_top.(3).cnf.cdb | 3KB |
uart_verilog/db/my_uart_top.(3).cnf.hdb | 1KB |
... |
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