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基于FPGA的IIC设计，Verilog.rar
资料介绍
基于FPGA的IIC设计，Verilog.rar 基于FPGA的IIC设计，Verilog.rar
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| IIC设计/i2c/i2c/bench/CVS/Entries | 1KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/bench/CVS/Repository | 1KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/bench/CVS/Root | 1KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/bench/verilog/CVS/Entries | 1KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/bench/verilog/CVS/Repository | 1KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/bench/verilog/CVS/Root | 1KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/bench/verilog/i2c_slave_model.v | 11KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/bench/verilog/spi_slave_model.v | 4KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/bench/verilog/tst_bench_top.v | 14KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/bench/verilog/wb_master_model.v | 5KB | 2013-04-22 20:33:22 |
| IIC设计/i2c/i2c/CVS/Entries | 1KB | 2013-04-22 20:33:22 |
| ... | ||
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