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智能卡芯片中ESD的设计
资料介绍
在智能卡的设计中,集成电路器件特征尺寸变得越来越小。目前主流的工艺是130 nm和90 nm,所面临的静电放电(ESD,Electro Static Discharge)挑战也越来越严峻。基于ESD研究背景,ESD故障机制和放电模型,ESD器件保护以及器件在布局上的ESD性能,对设计的ESD器件进行TLP实测,得出的结论在芯片的ESD设计中具有重要的参考意义。
In smart card design,the feature size of integrated circuit devices is becoming smaller and smaller.At present,the mainstream craftsmen at 130 and 90 nm are facing more and more severe challenges of electrostatic discharge(ESD).This paper will start with the background of ESD research,ESD fault mechanism and discharge model,ESD device protection and ESD performance in device layout.Finally,the ESD device is designed for TLP measurement,and the relevant conclusions are of great reference significance in the ESD design of the chip.
部分文件列表
| 文件名 | 大小 |
| 智能卡芯片中ESD的设计.pdf | 920K |
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