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cortex_m7_trm(Cortex-M7技术参考手册)

更新时间：2020-06-25 14:26:12 大小：1M 上传用户：xzxbybd查看TA发布的资源 标签：cortex-m7 下载积分：2分 评价赚积分 （如何评价?） 打赏 收藏 评论(0) 举报

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cortex_m7_trm(Cortex-M7技术参考手册)ARM Cortex-M7 Processor Technical ReferenceManual


The Cortex-M7 processor is a highly efficient high-performance, embedded processor that

features low interrupt latency, low-cost debug, and has backwards compatibility with existing

Cortex-M profile processors. The processor has an in-order super-scalar pipeline that means

many instructions can be dual-issued, including load/load and load/store instruction pairs

because of multiple memory interfaces.

Memory interfaces that the processor supports include:

• Tightly-Coupled Memory (TCM) interfaces.

• Harvard instruction and data caches and AXI master (AXIM) interface.

• Dedicated low-latency AHB-Lite peripheral (AHBP) interface.

• AHB-Lite slave (AHBS) interface that provides DMA access to TCMs.

The processor has an optional Memory Protection Unit (MPU) that you can configure to protect

regions of memory. Error Correcting Code (ECC) functionality for error detection and

correction, is included in the data and instruction caches when implemented. The TCM

interfaces support the implementation of external ECC to provide improved reliability and to

address safety-related applications.

The Cortex-M7 processor includes optional floating-point arithmetic functionality, with support

for single and double-precision arithmetic. See Chapter 8 Floating Point Unit.

The processor is intended for high-performance, deeply embedded applications that require fast

interrupt response features.

Figure 1-1 shows the processor in a typical system.


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