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ASIC电路中时钟驱动的抗单粒子加固

更新时间：2020-10-19 15:05:21 大小：280K 上传用户：gsy幸运查看TA发布的资源 标签：asic 电路时钟 下载积分：2分评价赚积分（如何评价?）收藏评论(0) 举报

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CMOS工艺制成的ASIC电路在太空中应用时,在辐射效应的影响下可能导致数据出错,影响整个系统的可靠性。在ASIC电路的抗辐射设计时,最关注的是时钟（CLK）驱动电路受辐射效应的影响。为此,文章分析了深亚微米工艺条件下CLK电路受到单粒子瞬态扰动效应（SET）的影响,为消除SET效应对CLK电路的扰动提出了四种加固方案,且分别介绍了四种方案的加固原理。通过对四种方案的抗辐射性能进行比较,得出在对ASIC时钟电路加固时,需要考虑功耗、延时等因素而采用不同策略。此工作为以后研制抗辐射ASIC电路提供了良好的借鉴和基础。

The ASICs which are made in CMOS technology suffer from the radiation effect when use in space.This leads to data mistakes,and influence the reliability of entire system.The radiation effect of CLK tree most attracts our eyes when our design the radiation hardness ASIC circuits.Therefore,we analyze the Single Event Transient influence of CLK tree in deep submicron process condition.For eliminating the upsets which is derived from SET in CLK tree,we put forward four hardened schemes,and the hardened principles are analyzed,respectively.Then,the performances of schemes are compared each other.It concludes that： the power,delay and other parameters should be tradeoff when in radiatio...