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Altera 官方PCI Express到DDR2 SDRAM 参考设计
资料介绍
Altera PCI Express到DDR2 SDRAM 参考设计
The Altera® PCI Express-to-DDR2 SDRAM reference design provides a
sample interface between the Altera PCI Express MegaCore® function
and a 64-bit, 256-MByte DDR2 SDRAM memory. Altera offers this
reference design to potential users to demonstrate the operation of
Altera's PCI Express MegaCore function. The reference design enables
users to evaluate the PCI Express MegaCore function for integration into
an Altera FPGA. The reference design has the following features:
■ Supports PCI Express (PCIe) root complex to PCIe end point
memory read and write transactions
■ Supports PCIe end point to PCIe root complex DMA read and write
transactions
■ Uses the dual-port FIFO buffer function from the library of
parameterized modules (LPM)
■ Uses the PCI Express MegaCore function
■ Uses the DDR2 SDRAM Controller MegaCore function
■ Uses the Stratix® II GX field-programmable gate array (FPGA) with
internal transceivers
This document contains the following topics:
部分文件列表
| 文件名 | 大小 |
| Altera_PCI_Express到DDR2_SDRAM_参考设计.pdf | 2M |
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