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FPGA读写 AD9708+ AD9280 ADDA实验Verilog逻辑源码Quartus工程源
资料介绍
FPGA读写 AD9708+ AD9280 ADDA实验Verilog逻辑源码Quartus工程源码文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8,Quartus版本17.1。
//2017/7/20 1.0 Original
//*******************************************************************************/
module top(
input clk,
input rst_n,
//adc
input[7:0] ad9280_data,
output ad9280_clk,
//dac
output[7:0] ad9708_data,
output ad9708_clk,
//vga output
output vga_out_hs, //vga horizontal synchronization
output vga_out_vs, //vga vertical synchronization
output[4:0] vga_out_r, //vga red
output[5:0] vga_out_g, //vga green
output[4:0] vga_out_b //vga blue
);
wire video_clk;
wire video_hs;
wire video_vs;
wire video_de;
wire[7:0] video_r;
wire[7:0] video_g;
wire[7:0] video_b;
wire grid_hs;
wire grid_vs;
wire grid_de;
wire[7:0] grid_r;
wire[7:0] grid_g;
wire[7:0] grid_b;
wire wave0_hs;
wire wave0_vs;
wire wave0_de;
wire[7:0] wave0_r;
wire[7:0] wave0_g;
wire[7:0] wave0_b;
wire adc_clk;
wire adc0_buf_wr;
wire[10:0] adc0_buf_addr;
wire[7:0] adc0_buf_data;
wire dac_clk;
wire[7:0] dac_data;
reg[8:0] rom_addr;
assign vga_out_hs = wave0_hs;
assign vga_out_vs = wave0_vs;
assign vga_out_r = wave
部分文件列表
文件名 | 大小 |
26.ADDA测试例程.pdf | 1220KB |
26_an108_adda_vga_test/ | |
26_an108_adda_vga_test/PLLJ_PLLSPE_INFO.txt | |
26_an108_adda_vga_test/an108_adda_vga_test.ipregen.rpt | 4KB |
26_an108_adda_vga_test/an108_adda_vga_test.jdi | 4KB |
26_an108_adda_vga_test/an108_adda_vga_test.qpf | |
26_an108_adda_vga_test/an108_adda_vga_test.qsf | 4KB |
26_an108_adda_vga_test/an108_adda_vga_test.sdc | 1KB |
26_an108_adda_vga_test/an108_adda_vga_test_assignment_defaults.qdf | |
26_an108_adda_vga_test/db/ | |
26_an108_adda_vga_test/db/.cmp.kpt | |
... |
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