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全桥LLCZVSSiC变换器样品设计
资料介绍
Over 1.2kV blocking voltage for conventional two-level converter and low Rdson to reduce conduction losses Low body diode t and Qr, which will reduce diode switching losses and electrical noise due to short reverse recovery time Lower turn off losses due to short fall time and low c Short turn off delay time can reduce dead time to improve efficiency Lower Qa will allow lower gate drive losses when switching frequency is high
部分文件列表
文件名 | 大小 |
全桥LLCZVSSiC变换器样品设计.pdf | 9M |
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