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设计的带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器
资料介绍
在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。.rar
部分文件列表
文件名 | 文件大小 | 修改时间 |
PCIe_Lab/.qsys_edit/filters.xml | 1KB | 2012-02-23 16:48:30 |
PCIe_Lab/.qsys_edit/preferences.xml | 1KB | 2012-02-23 17:14:12 |
PCIe_Lab/altgx_reconfig.v | 21KB | 2011-10-28 02:51:56 |
PCIe_Lab/c4gx_qsys/synthesis/c4gx_qsys.qip | 22KB | 2012-02-23 17:17:06 |
PCIe_Lab/c4gx_qsys/synthesis/c4gx_qsys.v | 459KB | 2012-02-23 17:14:52 |
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_avalon_mm_bridge.v | 11KB | 2012-02-23 17:16:16 |
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_avalon_sc_fifo.v | 31KB | 2012-02-23 17:15:50 |
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v | 5KB | 2012-02-23 17:15:52 |
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_avalon_st_pipeline_stage.sv | 5KB | 2012-02-23 17:15:54 |
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_irq_clock_crosser.sv | 2KB | 2012-02-23 17:15:54 |
PCIe_Lab/c4gx_qsys/synthesis/submodules/altera_merlin_arbitrator.sv | 9KB | 2012-02-23 17:15:54 |
... |
全部评论(2)
2023-01-10 21:58:18杨义
资料不错
2020-08-15 10:31:11suxindg
谢谢分享