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基于VHDL的时钟设计（de2开发平台）
资料介绍
基于VHDL的时钟设计（de2开发平台） 基于VHDL的时钟设计（de2开发平台）
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| FPGA-clock/clock-report.doc | 395KB | 2010-04-25 23:23:44 |
| FPGA-clock/jaymakenew/db/jaymake.db_info | 1KB | 2010-04-25 23:15:28 |
| FPGA-clock/jaymakenew/db/jaymake.eco.cdb | 1KB | 2010-04-25 23:16:12 |
| FPGA-clock/jaymakenew/db/jaymake.sim.vwf | 104KB | 2008-06-30 09:27:42 |
| FPGA-clock/jaymakenew/db/jaymake.sld_design_entry.sci | 1KB | 2010-04-25 23:16:12 |
| FPGA-clock/jaymakenew/db/wed.zsf | 1KB | 2008-07-04 18:00:52 |
| FPGA-clock/jaymakenew/decoder9.bsf | 2KB | 2008-06-30 09:42:50 |
| FPGA-clock/jaymakenew/divide50m.bsf | 2KB | 2008-06-30 09:42:50 |
| FPGA-clock/jaymakenew/divide50m.vhd | 1KB | 2008-06-29 10:50:54 |
| FPGA-clock/jaymakenew/jaymake.asm.rpt | 7KB | 2008-07-01 16:16:26 |
| FPGA-clock/jaymakenew/jaymake.bsf | 3KB | 2008-06-30 09:42:50 |
| ... | ||
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