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verilog hdl coding DDR sdram control for fpga
资料介绍
verilog hdl coding DDR sdram control for fpga
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| ddr_ctrl/.svn/text-base/ddr_top.v.svn-base | 9KB | 2007-07-20 17:27:28 |
| ddr_ctrl/.svn/text-base/ddr_par.v.svn-base | 9KB | 2007-07-20 17:27:28 |
| ddr_ctrl/.svn/text-base/ddr_sig.v.svn-base | 9KB | 2007-07-20 17:27:28 |
| ddr_ctrl/.svn/text-base/ddr_ctrl.v.svn-base | 15KB | 2007-07-20 17:27:28 |
| ddr_ctrl/.svn/text-base/ddr_data.v.svn-base | 12KB | 2007-07-20 17:27:28 |
| ddr_ctrl/.svn/format | 1KB | 2007-07-20 17:27:28 |
| ddr_ctrl/.svn/all-wcprops | 1KB | 2007-07-20 17:27:28 |
| ddr_ctrl/.svn/entries | 1KB | 2007-07-20 17:27:28 |
| ddr_ctrl/ddr_top.v | 9KB | 2007-07-20 17:27:28 |
| ddr_ctrl/ddr_par.v | 9KB | 2007-07-20 17:27:28 |
| ddr_ctrl/ddr_sig.v | 9KB | 2007-07-20 17:27:28 |
| ... | ||
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