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Verilog FPGA SPI slave收发测试,有简单的协议,modelsim仿真通过.zip
资料介绍
Verilog FPGA SPI slave收发测试,有简单的协议,modelsim仿真通过.zip
部分文件列表
| 文件名 | 大小 |
| SPI_fpga_w_r_sigle/ | |
| SPI_fpga_w_r_sigle/SPI1.archive.rpt | 4KB |
| SPI_fpga_w_r_sigle/SPI1.done | |
| SPI_fpga_w_r_sigle/SPI1.eda.rpt | 3KB |
| SPI_fpga_w_r_sigle/SPI1.flow.rpt | 8KB |
| SPI_fpga_w_r_sigle/SPI1.map.rpt | |
| SPI_fpga_w_r_sigle/SPI1.map.smsg | |
| SPI_fpga_w_r_sigle/SPI1.map.summary | |
| SPI_fpga_w_r_sigle/SPI1.qpf | 1KB |
| SPI_fpga_w_r_sigle/SPI1.qsf | 3KB |
| SPI_fpga_w_r_sigle/SPI1.qws | 1KB |
| ... | |
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