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verilog数字系统设计第二版 Verilog Digital System Design 2nd.pdf

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经典的verilog数字系统设计第二版的英文原版, pdf高清,内容涵盖了verilog语言精髓,组合顺序电路设计要点,以及模块化测试验证的要点内容.

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and Verification  
Zainalabedin Navabi, Ph.D.  
Professor of Electrical and Computer Engineering  
Northeastern University  
Boston, Massachusetts  
Second Edition  
McGraw-Hill  
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DOI: 10.1036/0071445641  
Professional  
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To my mother, Sadri Kheradmand (Navabi),  
who inspired me to pursue a life of science  
and engineering.  
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For more information about this title, click here  
Contents  
Preface  
xiii  
Chapter 1. Digital System Design Automation with Verilog  
1.1 Digital Design Flow  
1
2
1.1.1 Design entry  
1.1.2 Testbench in Verilog  
1.1.3 Design validation  
3
4
4
1.1.4 Compilation and synthesis  
1.1.5 Postsynthesis simulation  
1.1.6 Timing analysis  
7
10  
10  
10  
1.1.7 Hardware generation  
1.2 Verilog HDL  
10  
1.2.1 Verilog evolution  
1.2.2 Verilog attributes  
1.2.3 The Verilog language  
11  
11  
13  
1.3 Summary  
Problems  
13  
13  
14  
Suggested Reading  
Chapter 2. Register Transfer Level Design with Verilog  
2.1 RT Level Design  
15  
15  
2.1.1 Control/data partitioning  
2.1.2 Data part  
2.1.3 Control part  
16  
16  
17  
2.2 Elements of Verilog  
18  
2.2.1 Hardware modules  
2.2.2 Primitive instantiations  
2.2.3 Assign statements  
2.2.4 Condition expression  
2.2.5 Procedural blocks  
2.2.6 Module instantiations  
18  
19  
20  
20  
20  
21  
2.3 Component Description in Verilog  
22  
v
vi  
Contents  
2.3.1 Data components  
2.3.2 Controllers  
2.4 Testbenches  
22  
29  
33  
2.4.1 A simple tester  
2.4.2 Tasks and functions  
33  
34  
2.5 Summary  
34  
35  
35  
Problems  
Suggested Reading  
Chapter 3. Verilog Language Concepts  
3.1 Characterizing Hardware Languages  
37  
37  
3.1.1 Timing  
3.1.2 Concurrency  
3.1.3 Timing and concurrency example  
37  
39  
40  
3.2 Module Basics  
41  
3.2.1 Code format  
3.2.2 Logic value system  
3.2.3 Wires and variables  
3.2.4 Modules  
3.2.5 Module ports  
3.2.6 Names  
3.2.7 Numbers  
3.2.8 Arrays  
3.2.9 Verilog operators  
3.2.10 Verilog data types  
3.2.11 Array indexing  
41  
41  
42  
42  
43  
43  
44  
46  
48  
54  
58  
3.3 Verilog Simulation Model  
59  
3.3.1 Continuous assignments  
3.3.2 Procedural assignments  
61  
65  
3.4 Compiler Directives  
71  
3.4.1 `timescale  
3.4.2 `default-nettype  
3.4.3 `include  
71  
71  
71  
71  
72  
72  
72  
72  
3.4.4 `define  
3.4.5 `ifdef, `else, `endif  
3.4.6 `unconnected-drive  
3.4.7 `celldefine, `endcelldefine  
3.4.8 `resetall  
3.5 System Tasks and Functions  
72  
3.5.1 Display tasks  
3.5.2 File I/O tasks  
3.5.3 Timescale tasks  
3.5.4 Simulation control tasks  
3.5.5 Timing check tasks  
3.5.6 PLA modeling tasks  
3.5.7 Conversion functions for reals  
3.5.8 Other tasks and functions  
73  
73  
74  
74  
74  
74  
75  
75  
3.6 Summary  
Problems  
76  
76  
80  
Suggested Reading  
Contents  
vii  
Chapter 4. Combinational Circuit Description  
4.1 Module Wires  
81  
81  
4.1.1 Ports  
81  
82  
82  
84  
4.1.2 Interconnections  
4.1.3 Wire values and timing  
4.1.4 A simple testbench  
4.2 Gate Level Logic  
85  
4.2.1 Gate primitives  
4.2.2 User defined primitives  
4.2.3 Delay formats  
85  
87  
88  
90  
4.2.4 Module parameters  
4.3 Hierarchical Structures  
93  
4.3.1 Simple hierarchies  
4.3.2 Vector declarations  
4.3.3 Iterative structures  
4.3.4 Module path delay  
93  
95  
96  
99  
4.4 Describing Expressions with Assign Statements  
102  
4.4.1 Bitwise operators  
4.4.2 Concatenation operators  
4.4.3 Vector operations  
4.4.4 Conditional operation  
4.4.5 Arithmetic expressions in assignments  
4.4.6 Functions in expressions  
4.4.7 Bus structures  
102  
104  
104  
105  
108  
109  
110  
111  
4.4.8 Net declaration assignment  
4.5 Behavioral Combinational Descriptions  
112  
4.5.1 Simple procedural blocks  
4.5.2 Timing control  
4.5.3 Intra-assignment delay  
4.5.4 Blocking and nonblocking assignments  
4.5.5 Procedural if-else  
4.5.6 Procedural case statement  
4.5.7 Procedural for statement  
4.5.8 Procedural while loop  
4.5.9 A multilevel description  
113  
113  
116  
116  
118  
120  
122  
123  
124  
4.6 Combinational Synthesis  
125  
4.6.1 Gate level synthesis  
4.6.2 Synthesizing continuous assignments  
4.6.3 Behavioral synthesis  
127  
128  
129  
132  
4.6.4 Mixed synthesis  
4.7 Summary  
Problems  
132  
132  
134  
Suggested Reading  
Chapter 5. Sequential Circuit Description  
5.1 Sequential Models  
135  
135  
5.1.1 Feedback model  
5.1.2 Capacitive model  
5.1.3 Implicit model  
136  
136  
136  
viii  
Contents  
5.2 Basic Memory Components  
137  
5.2.1 Gate level primitives  
137  
139  
140  
142  
149  
151  
5.2.2 User defined sequential primitives  
5.2.3 Memory elements using assignments  
5.2.4 Behavioral memory elements  
5.2.5 Flip-Flop timing  
5.2.6 Memory vectors and arrays  
5.3 Functional Registers  
157  
5.3.1 Shift registers  
5.3.2 Counters  
5.3.3 LFSR and MISR  
5.3.4 Stacks and queues  
157  
161  
163  
167  
5.4 State Machine Coding  
171  
5.4.1 Moore machines  
5.4.2 Mealy machines  
5.4.3 Huffman coding style  
5.4.4 A more modular style  
5.4.5 A ROM based controller  
171  
174  
176  
180  
181  
5.5 Sequential Synthesis  
181  
5.5.1 Latch models  
5.5.2 Flip-flop models  
5.5.3 Memory initialization  
5.5.4 General sequential circuit synthesis  
183  
184  
185  
186  
5.6 Summary  
Problems  
186  
187  
189  
Suggested Reading  
Chapter 6. Component Test and Verification  
6.1 Testbench  
191  
191  
6.1.1 Combinational circuit testing  
6.1.2 Sequential circuit testing  
192  
194  
6.2 Testbench Techniques  
195  
6.2.1 Test data  
6.2.2 Simulation control  
6.2.3 Limiting data sets  
6.2.4 Applying synchronized data  
6.2.5 Synchronized display of results  
6.2.6 An interactive testbench  
6.2.7 Random time intervals  
6.2.8 Buffered data application  
196  
197  
198  
199  
200  
201  
204  
205  
6.3 Design Verification  
206  
6.4 Assertion Verification  
207  
6.4.1 Assertion verification benefits  
6.4.2 Open verification library  
6.4.3 Using assertion monitors  
6.4.4 Assertion templates  
208  
208  
209  
216  
6.5 Text Based Testbenches  
219  
6.6 Summary  
Problems  
220  
220  
221  
Suggested Reading  

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  • 2019-10-10 10:36:27suxindg

    谢谢分享