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SystemVerilog快速语法参考
资料介绍
Introduction System Verilog is a standard (IEEE std 1800-2005)unified hardware design, specification,and verification language,which provides a set of extensions to the IEEE 1364 Verilog HDL:
·design specification method for both abstract and detailed specifications
·embedded assertions language and application programming interface
(API)for coverage and assertions
·testbench language based on manual and autom atic methodologies
·direct programming interface(DPI)
Purpose:provide a standard which improves productivity,readability,and reusability of Verilog-based code,extends for higher level of abstraction for system modeling and verification,provides extensive support for directed and constrained-random testbench development,coverage-driven verification,and form al assertion-based verification
部分文件列表
| 文件名 | 大小 |
| SystemVerilog快速语法参考.pdf | 2M |
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