Technical Note 15
1(5)
SPI Interface Specification
OBJECTIVE
This document specifies the Serial Peripheral Interface (SPI) that is used in the SCA61T, SCA100T,
SCA103T, SCA1000, and SCA1020 – series sensors.
THE SPI INTERFACE
A Serial Peripheral Interface (SPI) system consists of one master device and one or more slave devices. The
master is defined as a microcontroller providing the SPI clock and the slave as any integrated circuit receiving
the SPI clock from the master. The ASIC in VTI Technologies
master-slave operation mode.
’ products always operates as a slave device in
The SPI has a 4-wire synchronous serial interface. Data communication is enabled with a low active Slave
Select or Chip Select wire (CSB). Data is transmitted with a 3-wire interface consisting of wires for serial data
input (MOSI), serial data output (MISO) and serial clock (SCK).
MASTER
SLAVE
SI
MICROCONTROLLER
DATA OUT (MOSI)
DATA IN (MISO)
SO
SERIAL CLOCK (SCK)
SCK
SS0
SS1
CS
SI
SS2
SS3
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
Figure 1. Typical SPI connection
The SPI interface in VTI products is designed to support any microcontroller that uses SPI bus.
Communication can be carried out by software or hardware based SPI. Please note that in the case of
hardware based SPI, the received acceleration data is 11 bits. The SPI interface is used for testing and
calibration purposes, and it can also be used in the final application. Some of the test and calibration
commands are disabled in normal use, and are not documented here
wire interface:
. The data transfer uses the following 4-
MOSI
master out slave in
master in slave out
clock
μP → ASIC
ASIC → μP
μP → ASIC
μP → ASIC
MISO
SCK serial
CSB
chip select (low active)
19 Sep 2005
VTI Technologies reserves all rights to modify this document without prior notice.
全部评论(2)
2022-05-18 16:55:25wuqi8
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2022-03-29 08:50:4121iscolor
挺详细的参考有用