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MBD-FPGA数字滤波器设计基本流程,基于DSP builder.rar
资料介绍
MBD-FPGA数字滤波器设计基本流程,基于DSP builder.rar
部分文件列表
文件名 | 文件大小 | 修改时间 |
filter design/AutoGentorCoSimulation.mdl | 683KB | 2011-10-26 19:33:42 |
filter design/compile_and_launch.tcl | 5KB | 2011-10-26 19:33:18 |
filter design/hdlsrc/filter_Hf2.v | 67KB | 2011-10-26 19:33:40 |
filter design/hdlsrc/filter_Hf2_compile.do | 1KB | 2011-10-26 19:33:40 |
filter design/hdlsrc/filter_Hf2_generatehdl.m | 1KB | 2011-10-26 19:33:40 |
filter design/hdlsrc/transcript | 3KB | 2011-10-27 14:58:42 |
filter design/hdlsrc/vsim.wlf | 128KB | 2011-10-26 19:33:46 |
filter design/hdlsrc/work/filter_@hf2/verilog.prw | 70KB | 2011-10-27 14:58:40 |
filter design/hdlsrc/work/filter_@hf2/verilog.psm | 506KB | 2011-10-27 14:58:40 |
filter design/hdlsrc/work/filter_@hf2/_desktop.ini | 1KB | 2011-11-21 08:23:22 |
filter design/hdlsrc/work/filter_@hf2/_primary.dat | 56KB | 2011-10-27 14:58:42 |
... |
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