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用VerilogHDL编写的DDR3控制器，使用了自带的IP核生成mig来进行读写
资料介绍
用VerilogHDL编写的DDR3控制器，使用了自带的IP核生成mig来进行读写
部分文件列表
| 文件名 | 大小 |
| mig_33/example_design/par/ML605_SODIMM_example_design.cpj | |
| mig_33/example_design/par/example_top.ucf | |
| mig_33/example_design/par/set_ise_prop.tcl | |
| mig_33/example_design/rtl/ip_top/dbg_display_driver.v | |
| mig_33/example_design/rtl/ip_top/example_top.v | |
| mig_33/example_design/rtl/ip_top/iodelay_ctrl.v | 8KB |
| mig_33/example_design/synth/example_top.prj | 3KB |
| mig_33/example_design/synth/synplify_pro.tcl | 5KB |
| ml605_prebuilt_example_design/mig_33.gise | 1KB |
| ml605_prebuilt_example_design/mig_33.ise | |
| ml605_prebuilt_example_design/mig_33.veo | |
| ... | |
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