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如何进行设计优化(一个IC设计优化的实例)
资料介绍
A wealth of new hierarchical compile strategies have become available in the last few years.This
paper will compare area,speed,and compile time for several large designs using a variety of
hierarchical compile strategies: top-down compile,top-down simple compile,bottom-up with
default constraints,bottom-up with hand-crafted constraints,and ACS(Automated Chip
Synthesis).
部分文件列表
| 文件名 | 大小 |
| 如何进行设计优化(一个IC设计优化的实例).pdf | 132K |
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