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FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，
资料介绍
FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| cpu_design/top.lso | 1KB | 2014-07-04 09:19:46 |
| cpu_design/top.ngr | 1KB | 2014-07-04 09:19:48 |
| cpu_design/top.ngc | 5KB | 2014-07-04 09:19:58 |
| cpu_design/cpu_design.xise | 39KB | 2014-07-04 15:36:50 |
| cpu_design/top.prj | 1KB | 2014-07-04 09:19:40 |
| cpu_design/xst/work/work.sdbl | 37KB | 2014-07-04 09:19:46 |
| cpu_design/xst/work/work.sdbx | 1KB | 2014-07-04 09:19:46 |
| cpu_design/top.xst | 1KB | 2014-07-04 09:19:40 |
| cpu_design/top_xst.xrpt | 13KB | 2014-07-04 09:19:58 |
| cpu_design/top.syr | 93KB | 2014-07-04 09:19:58 |
| cpu_design/xilinxsim.ini | 1KB | 2014-07-10 15:50:36 |
| ... | ||
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