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FPGA之间的LVDS传输，采用serdes接口
资料介绍
FPGA之间的LVDS传输，采用serdes接口
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| LVDS_Serdes_list_FPGA1/bit_align_machine.bgn | 6KB | 2008-08-19 19:52:56 |
| LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.bld | 1KB | 2008-08-19 20:15:16 |
| LVDS_Serdes_list_FPGA1/bit_align_machine.drc | 1KB | 2008-08-19 19:52:42 |
| LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.ncd | 33KB | 2008-08-19 20:17:00 |
| LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.ngd | 37KB | 2008-08-19 20:15:14 |
| LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.pad | 39KB | 2008-08-19 20:16:58 |
| LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.par | 5KB | 2008-08-19 20:17:00 |
| LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.pcf | 1KB | 2008-08-19 20:16:10 |
| LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.ptwx | 17KB | 2008-08-19 20:16:46 |
| LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.twr | 4KB | 2008-08-19 20:17:20 |
| LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.twx | 21KB | 2008-08-19 20:17:20 |
| ... | ||
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