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FPGA门电路实现的8位乘法器, Verilog 语言编写，ISE平台
资料介绍
FPGA门电路实现的8位乘法器, Verilog 语言编写，ISE平台
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| Multiplier/fuse.log | 1KB | 2016-10-04 19:01:58 |
| Multiplier/fuse.xmsgs | 1KB | 2016-10-04 19:01:58 |
| Multiplier/fuseRelaunch.cmd | 1KB | 2016-10-04 19:01:58 |
| Multiplier/iseconfig/Multiplier.projectmgr | 7KB | 2016-10-04 20:18:24 |
| Multiplier/iseconfig/Multiplier.xreport | 20KB | 2016-10-02 21:10:36 |
| Multiplier/iseconfig/Multiplier_re.xreport | 20KB | 2016-10-04 20:16:46 |
| Multiplier/isim/isim_usage_statistics.html | 1KB | 2016-10-04 19:01:58 |
| Multiplier/isim/Multiplier_tb_isim_beh.exe.sim/isimcrash.log | 1KB | 2016-10-04 20:16:58 |
| Multiplier/isim/Multiplier_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg | 5KB | 2016-10-04 20:16:58 |
| Multiplier/isim/Multiplier_tb_isim_beh.exe.sim/isimkernel.log | 1KB | 2016-10-04 21:00:54 |
| Multiplier/isim/pn_info | 1KB | 2016-10-04 19:01:56 |
| ... | ||
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