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CAN总线的FPGA实现,用Verilog编写,代码完整,而且有很完善的测试代码
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CAN总线的FPGA实现,用Verilog编写,代码完整,而且有很完善的测试代码,用ISE直接打开,学习FPGA进阶的好项目
部分文件列表
文件名 | 文件大小 | 修改时间 |
canbus/.untf | 1KB | 2005-01-11 10:14:24 |
canbus/automake.log | 1KB | 2005-04-12 09:15:14 |
canbus/canbus.dhp | 17KB | 2005-01-11 10:21:26 |
canbus/canbus.npl | 1KB | 2005-04-12 09:15:14 |
canbus/can_acf.v | 14KB | 2005-04-12 09:10:28 |
canbus/can_bsp.v | 51KB | 2005-04-12 09:10:02 |
canbus/can_btl.v | 6KB | 2005-04-12 09:13:14 |
canbus/can_crc.v | 1KB | 2005-04-12 09:10:44 |
canbus/can_defines.v | 1KB | 2005-04-13 23:51:52 |
canbus/can_fifo.cmd_log | 1KB | 2005-01-11 09:21:34 |
canbus/can_fifo.lso | 1KB | 2005-01-11 09:21:36 |
... |
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