推荐星级:
  • 1
  • 2
  • 3
  • 4
  • 5

Alteral FPGA VERILOG实现高速到低速时钟域的数据传输

更新时间:2019-11-12 19:13:22 大小:907K 上传用户:zyf901126查看TA发布的资源 标签:alteralfpgaverilog数据传输 下载积分:9分 评价赚积分 (如何评价?) 收藏 评论(0) 举报

资料介绍

Alteral FPGA VERILOG实现高速到低速时钟域的数据传输

image.png

部分文件列表

文件名文件大小修改时间
an_dcfifo_top_restored/an473.pdf1328KB2008-08-27 15:54:26
an_dcfifo_top_restored/an_dcfifo_top.qarlog1KB2008-08-27 15:58:12
an_dcfifo_top_restored/an_dcfifo_top.qpf1KB2007-11-29 16:36:40
an_dcfifo_top_restored/an_dcfifo_top.qsf4KB2008-08-27 15:58:18
an_dcfifo_top_restored/an_dcfifo_top.qws1KB2008-08-27 17:09:18
an_dcfifo_top_restored/an_dcfifo_top.v2KB2007-11-09 14:40:30
an_dcfifo_top_restored/an_dcfifo_top_assignment_defaults.qdf32KB2007-10-04 16:44:26
an_dcfifo_top_restored/an_dcfifo_top_fast_to_slow.sdc4KB2007-11-29 16:34:14
an_dcfifo_top_restored/an_dcfifo_top_fast_to_slow.vwf22KB2007-11-06 13:43:34
an_dcfifo_top_restored/an_dcfifo_top_slow_to_fast.sdc4KB2007-11-29 16:35:08
an_dcfifo_top_restored/an_dcfifo_top_slow_to_fast.vwf22KB2007-11-06 13:44:34
...

全部评论(0)

暂无评论