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Alteral FPGA VERILOG实现高速到低速时钟域的数据传输
资料介绍
Alteral FPGA VERILOG实现高速到低速时钟域的数据传输
部分文件列表
文件名 | 文件大小 | 修改时间 |
an_dcfifo_top_restored/an473.pdf | 1328KB | 2008-08-27 15:54:26 |
an_dcfifo_top_restored/an_dcfifo_top.qarlog | 1KB | 2008-08-27 15:58:12 |
an_dcfifo_top_restored/an_dcfifo_top.qpf | 1KB | 2007-11-29 16:36:40 |
an_dcfifo_top_restored/an_dcfifo_top.qsf | 4KB | 2008-08-27 15:58:18 |
an_dcfifo_top_restored/an_dcfifo_top.qws | 1KB | 2008-08-27 17:09:18 |
an_dcfifo_top_restored/an_dcfifo_top.v | 2KB | 2007-11-09 14:40:30 |
an_dcfifo_top_restored/an_dcfifo_top_assignment_defaults.qdf | 32KB | 2007-10-04 16:44:26 |
an_dcfifo_top_restored/an_dcfifo_top_fast_to_slow.sdc | 4KB | 2007-11-29 16:34:14 |
an_dcfifo_top_restored/an_dcfifo_top_fast_to_slow.vwf | 22KB | 2007-11-06 13:43:34 |
an_dcfifo_top_restored/an_dcfifo_top_slow_to_fast.sdc | 4KB | 2007-11-29 16:35:08 |
an_dcfifo_top_restored/an_dcfifo_top_slow_to_fast.vwf | 22KB | 2007-11-06 13:44:34 |
... |
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